1. Field of the Invention
Example embodiments of the present invention generally relate to a method of monitoring a dynamic temperature of a semiconductor memory system and a semiconductor memory system. More particularly, example embodiments of the present invention relate to a method of monitoring a dynamic temperature of a fully-buffered memory module, and the fully-buffered memory module.
2. Description of the Related Art
There are two reasons why dynamic temperatures of a Dynamic Random Access Memory (DRAM) device should be monitored.
The first reason is to reduce power consumption of the DRAM chip using a method similar to a temperature-compensated self-refresh (TCSR).
A memory cell of the DRAM chip records data by storing a charge in a cell capacitor. However, the charge in the cell capacitor may be lost over time due to a leakage current when no read/write operations take place. Hence, a refresh process configured to periodically rewrite data stored in the cell capacitor is needed. A refresh period may be defined as a time interval for refreshing the cell capacitor in the DRAM chip. The longer the refresh period is, the less a DRAM chip consumes power. Recently, manufactured DRAM chips have used Temperature-Compensated Self-Refresh (TCSR) to increase the self-refresh period. TCSR uses an embedded temperature sensor to measure an inner temperature of the DRAM chip and change the self-refresh period based on the measured temperature. The leakage current in the cell capacitor has a very strong dependency on temperature. Thus, when the temperature sensor detects a low temperature, a long refresh period may be maintained to reduce power consumption.
A second reason is that dynamic temperature monitoring may be necessary to determine an operating speed range, which may guarantee a reliability of the DRAM chip.
For example, when an inner temperature of the DRAM chip is above a specific threshold temperature, reliability of the DRAM chip may be guaranteed by decreasing the operation speed of the DRAM chip at the temperature.
Here, a temperature sensor may be used for the purpose of reducing the power consumption. It may not be necessary to transmit the measured temperature information exterior to the DRAM chip, because the temperature sensor may only be used internally. Therefore, the temperature sensor may be integrated into the DRAM chip to directly measure the temperature of the DRAM chip. Because it may not be necessary to communicate temperature information to an exterior of the DRAM chip, communications-related compatibility problems may not exist on an operational side.
However, to guarantee the operational reliability of a DRAM chip, the measured temperature information should be externally monitored, and thus, there may be a need for an operational method capable of transmitting the temperature information to the exterior of the DRAM chip without interrupting basic operations of the DRAM, for example, read operation and/or write operation.
The bandwidth throttling method may be used to overcome the above problem. The bandwidth throttling method controls an operational bandwidth based on a relationship between the operational bandwidth and a temperature instead of directly measuring a temperature by using temperature sensors. The relationship is a function of a current of a semiconductor chip and a temperature characteristic of a semiconductor package.
The bandwidth throttling method has the advantage of being easy to use because it indirectly uses the temperature sensor. However, it may be difficult to adapt the bandwidth throttling method to all of the various memory access types of DRAM devices. That is, there may be a negative effect in that if the bandwidth throttling method is used to set a threshold bandwidth to low level, when lowering of the threshold bandwidth may not be required, a general performance level of the DRAM may decrease.
A DRAM memory module having a plurality of memory devices mounted on a printed circuit board (PCB) may be classified as either a Single In-line Memory Module (SIMM) or a Dual In-line Memory Module (DIMM). A DIMM is one of the most commonly used types of memory module, and may be further classified as either a Fully-Buffered Dual In-line Memory Module (FB-DIMM) or a Registered DIMM. Recently, practical application research for the FB-DIMM has increased in an effort to obtain a high-speed and high-capacity memory system. A memory system including the FB-DIMM may include a plurality of slots on a motherboard for FB-DIMM insertion.
FIG. 1 is a block diagram illustrating a conventional memory system including Fully-Buffered Dual In-line Memory Modules (FB-DIMMs).
Referring to FIG. 1, a FB-DIMM memory system 100 may include a host 110 and a plurality of FB-DIMMs (MM1, . . . , MMn, n may be a natural number) connected in a daisy chain. In general, up to eight (8) FB-DIMMs (MM1, . . . , MMn) may be connected in the daisy chain.
The host 110 may include a transmitter (STx) to transmit southbound (SB) packets to the plurality of FB-DIMMs (MM1, . . . , MMn), and a receiver (NRx) to receive northbound (NB) packets that may be transferred from the plurality of FB-DIMMs to the host 110.
The FB-DIMMs (MM1, . . . , MMn) may include a memory hub (120-1, . . . , 120-n) and a plurality of DRAM devices (M1, . . . , Mm, m may be a natural number). Each memory hub may include an SB packet transceiver (STx/SRx), an NB packet transceiver (NTx/NRx), and a memory hub control block 122. Although not shown in FIG. 1, each of the memory hubs (120-1, . . . , 120-n) may include a System Management Bus (SMBus) interface block, and may be connected with the host 110 through a SMBus. Therefore, the host 110 may control the memory hubs (120-1, . . . , 120-n) through the SMBus.
The SB packet receiver (SRx) may receive a high-speed SB packet transferred from the host 110 or from an adjacent FB-DIMM located in an opposite direction to that of the SB packet's transmission. In contrast, the SB packet transmitter (STx) may transmit the SB packet received at the SB packet receiver (SRx) to an adjacent FB-DIMM located in the same direction as that of the SB packet's transmission.
The memory hub control block 122 may decode the SB packet received at the SB packet receiver (SRx); may generate command and address information for the DRAM devices (M1, . . . , Mm); may write data and read data; may encode the read data into an NB packet; and may transmit the NB packet through the NB packet transmitter (NTx).
The NB packet receiver (NRx) may receive a high-speed NB packet transferred from an adjacent FB-DIMM located in an opposite direction of the NB packet's transmission. In contrast, the NB packet transmitter (NTx) may transmit the NB packet received at the NB packet receiver (NRx) to the host 110 or an adjacent FB-DIMM located in the same direction as the NB packet's transmission.
In addition, each memory hub (120-1, . . . , 120-n) may include a memory interface block 124 to interface with the DRAM devices (M1, . . . , Mm). A FB-DIMM memory system 100 may use a memory hub, for example, an Advanced Memory Buffer (AMB), to buffer input/output data of DRAM devices instead of using a direct connection between the DRAM devices and a memory controller. However, a FB-DIMM memory system does not have temperature monitoring capabilities.